1. Field of the Invention
The present invention relates to a motion picture processing device which processes a motion picture in real time by pipeline processing, and in particular, relates to processing at the time when a failure, in which processing of image data is not completed within a prescribed time period, arises.
2. Description of the Related Art
FIG. 2 is a structural view of a conventional motion picture processing device.
This motion picture processing device processes and encodes, in real time, image data which is outputted from a video camera. The motion picture processing device has: a pipeline processing circuit formed by an input circuit 10, a motion estimation circuit 20 and an encoding circuit 30; a memory 40 which is used as a buffer for the transfer of data which is being processed in the pipeline processing; and a memory control circuit 50. The input circuit 10, the motion estimation circuit 20, and the encoding circuit 30 are connected to the memory control circuit 50 via a bus 60. Further, the motion picture processing device has a failure control circuit 70 which effects control such that the pipeline processing does not fall into an abnormal state.
The input circuit 10 takes-in an image signal VIN supplied from a video camera, and writes image data in the memory 40 in units of one frame. The input circuit 10 has: a synchronization detecting section 11 detecting and outputting a vertical synchronous signal SYN from the image signal VIN; an image data taking-in section 12 which takes-in the image data which is in the image signal VIN in accordance with a start signal STA supplied from the failure control circuit 70; a buffer memory 13 temporarily holding the taken-in image data; and a bus interface (hereinafter called “bus I/F”) 14 for writing the image data, which is held in the buffer memory 13, to the memory 40 via the bus 60. At the point in time when the bus I/F 14 writes, to the memory 40, the image data of one frame which is in the buffer memory 13, the bus I/F 14 outputs an end signal END1 to the failure control circuit 70.
The motion estimation circuit 20 carries out motion searching with respect to the image data which the input circuit 10 and the encoding circuit 30 write to the memory 40, and outputs the results thereof to the memory 40. The encoding circuit 30 carries out encoding processing other than the motion searching, and generates MPEG-4 (Motion Picture Expert Group 4) encoded data and writes the reconstructed image to the memory 40, and outputs it as output data OUT. The motion estimation circuit 20 and the encoding circuit 30 start processings in accordance with the start signal STA supplied from the failure control circuit 70, and, at the points in time when the processings thereof end, output end signals END2, END3, respectively, to the failure control circuit 70.
The memory 40 is a 3-bank structure of banks BK1, BK2, BK3, and data needed for the processing of image data of one frame is written to each of the banks BK1 through BK3. Further, the respective circuits which are the input circuit 10, the motion estimation circuit 20, and the encoding circuit 30 use the banks in order from the bank BK1, and, when the bank BK3 is used, the bank BK1 is used again.
On the other hand, when the failure that the processing of the image data is not completed within the prescribed time period arises, the failure control circuit 70 prevents the pipeline processing from falling into an abnormal state by stopping output of the start signal STA. For example, the failure control circuit 70 has an AND gate (hereinafter called “AND”) 71 which gate-controls, by an operation enabling signal ENA, the vertical synchronous signal SYN supplied from the input circuit 10, and supplies it as the start signal STA to the input circuit 10, the motion estimation circuit 20, and the encoding circuit 30.
The start signal STA is supplied to set terminals S of set-reset-type flip-flops (hereinafter called “FFs”) 72a, 72b, 72c within the failure control circuit 70. The end signals END1 through END3 from the input circuit 10, the motion estimation circuit 20, and the encoding circuit 30 are supplied to reset terminals R of the FFs 72a through 72c via two-input OR gates (hereinafter called “ORs”) 73a, 73b, 73c, respectively. Further, a system reset signal RST is supplied to the other input sides of the ORs 73a through 73c. The output sides of the FFs 72a through 72c are connected to a three-input NOR gate (hereinafter called “NOR”) 74. The operation enabling signal ENA is outputted from the NOR 74 and is supplied to the AND 71.
FIG. 3 is a signal waveform diagram showing the operation of FIG. 2. Hereinafter, operation of FIG. 2 will be described with reference to FIG. 3.
Image data #1, #2, #3, . . . , which are sectioned from the video camera into respective one frames in vertical synchronization, are supplied to the input circuit 10 at constant periods as the image signal VIN. At the synchronization detecting section 11, the vertical synchronization intervals, in which the image data #1, #2, #3 . . . do not exist, in the image signal VIN are detected, and the vertical synchronous signal SYN is outputted to the failure control circuit 70 at constant periods.
The FFs 72a through 72c within the failure control circuit 70 are all reset by the system reset signal RST which is supplied at the time when operation starts. Therefore, the operation enabling signal ENA outputted from the NOR 74 is level “H”. In this way, the start signal STA is outputted from the AND 71 at the same timing as the vertical synchronous signal SYN, and is supplied to the input circuit 10, the motion estimation circuit 20, and the encoding circuit 30. The start signal STA is further supplied to the FFs 72a through 72c, these FFs 72a through 72c are reset, and the operation enabling signal ENA becomes level “L”.
When the image data #1 is taken-in by the image data taking-in section 12, the input circuit 10 starts inputting processing, such as writing the image data #1 to the bank BK1 of the memory 40, and the like. On the other hand, at the motion estimation circuit 20 and the encoding circuit 30, because image data to be processed does not exist, the end signals END1, END2 are outputted immediately. In this way, the FFs 72b, 72c are reset. When the input circuit 10 has taken-in all of the image data #1 and written it to the bank BK1 of the memory 40, the input circuit 10 outputs the end signal END1, and the FF 72a is reset. In this way, the operation enabling signal ENA becomes “H”.
Due to the start signal STA corresponding to the next vertical synchronous signal SYN, the input circuit 10 carries out inputting processing of taking-in the image data #2 and writing it to the bank BK2 of the memory 40, and the motion estimation circuit 20 carries out motion estimation processing with respect to the image data #1 in the bank BK1. On the other hand, at the encoding circuit 30, because image data to be processed does not exist, the end signal END2 is outputted immediately. At the points in time when their respective processings are ended, the input circuit 10 and the motion estimation circuit 20 output the end signals END1, END2.
Due to the start signal STA corresponding to the next vertical synchronous signal SYN, the input circuit 10 carries out inputting processing of taking-in the image data #3 and writing it to the bank BK3, and the motion estimation circuit 20 carries out motion estimation processing with respect to the image data #2 in the bank BK2. On the other hand, the encoding circuit 30 carries out encoding processing of the image data #1 in the bank BK1, and outputs it as the output data OUT. At the points in time when their respective processings are ended, the input circuit 10, the motion estimation circuit 20, and the encoding circuit 30 output the end signals END1, END2, END3.
Here, if the processing of the motion estimation circuit 20 is delayed due to competition of the bus 60 or the like and is not finished by the time corresponding to the next vertical synchronous signal SYN, the FF 72b is not reset, and the operation enabling signal ENA remains “L”. Therefore, output of the next start signal STA is suppressed, and the inputting processing of image data #4 by the input circuit 10 cannot be carried out. Thereafter, at the point in time when the processing of the motion estimation circuit 20 is ended, the end signal END2 is outputted, and the operation enabling signal ENA becomes “H”.
Due to the start signal STA corresponding to the next vertical synchronous signal SYN, the input circuit 10 carries out the inputting processing of taking-in image data #5 and writing it to the bank BK1, and the motion estimation circuit 20 carries out motion estimation processing with respect to the image data #3 in the bank BK3, and the encoding circuit 30 carries out encoding processing of the image data #2 in the bank BK2 and outputs the output data OUT. Here, if the processing of the encoding circuit 30 is delayed due to competition of the bus 60 or the like and is not finished by the time corresponding to the next vertical synchronous signal SYN, the FF 72c is not reset, and the operation enabling signal ENA remains “L”. Therefore, output of the next start signal STA is suppressed, and the inputting processing of image data #6 by the input circuit 10 cannot be carried out. Thereafter, at the point in time when the processing of the encoding circuit 30 is finished, the end signal END3 is outputted, and the operation enabling signal ENA becomes “H”.
In this way, the motion picture processing device of FIG. 2 has the failure control circuit 70 which, when all of the processings of the input circuit 10, the motion estimation circuit 20, and the encoding circuit 30 are ended within the time period of one frame, outputs the operation enabling signal ENA for causing inputting processing of the next image data to be carried out. Therefore, if the failure that processing of the image data is not completed within a prescribed time period (the time period of one frame) arises, the pipeline processing can be prevented from falling into an abnormal state.
However, in the above-described motion picture processing device, if there exists even one circuit at which processing is not ended among the input circuit 10, the motion estimation circuit 20, and the encoding circuit 30, the processing of taking-in the next image data is suppressed. Therefore, the frequency of image data which is not taken-in and which is thinned-out becomes large, and there is the concern that the quality of the motion picture which is outputted as the output data OUT will deteriorate.